Memory provides data storage for electronic systems. Flash memory is one type of memory, and has numerous uses in modern computers and devices. For instance, modern personal computers may have BIOS stored on a flash memory chip. As another example, it is becoming increasingly common for computers and other devices to utilize flash memory in solid state drives to replace conventional hard drives. As yet another example, flash memory is popular in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized, and to provide the ability to remotely upgrade the devices for enhanced features.
NAND may be a basic architecture of flash memory. A NAND cell unit comprises at least one selecting device coupled in series to a serial combination of memory cells (with the serial combination commonly being referred to as a NAND string). Example NAND architecture is described in U.S. Pat. No. 7,898,850. NAND architecture may be configured to comprise vertically-stacked memory cells. Fabrication of the vertically-stacked memory cells may comprise forming openings through a tall stack of alternating electrically conductive levels and electrically insulative levels, which becomes increasingly difficult with higher aspect ratio and smaller critical dimensions of the openings. FIGS. 1 and 2 describe some of the difficulties encountered during fabrication of such openings
FIG. 1 shows a semiconductor construction 10 comprising a stack 16 of alternating electrically insulative levels 18 and electrically conductive levels 20. The electrically conductive levels 20 may comprise, for example, one or more of various metals (for example, tungsten, titanium, etc.), metal-containing compositions (for example, metal nitride, metal carbide, metal silicide, etc.), and conductively-doped semiconductor materials (for example, conductively-doped silicon, conductively-doped germanium, etc.). For instance, the electrically conductive levels 20 may comprise n-type doped polycrystalline silicon (i.e., n-type doped polysilicon). The electrically insulative levels 18 may, for example, comprise silicon dioxide.
The levels 18 and 20 may be of any suitable thicknesses; and may, for example, have thicknesses within a range of from about 10 nm to about 300 nm. In some applications, the levels 18 may be thinner than the levels 20. For instance, levels 18 may be about 20 nm thick and levels 20 may be about 30 nm thick.
The electrically conductive levels 20 may be utilized to pattern control gates of flash devices. In such applications, a vertical string of memory cells (such as, for example, a vertical NAND string of memory cells) may be fabricated, with the number of memory cells in each string being determined by the number of electrically conductive levels 20. The stack may comprise any suitable number of electrically conductive levels. For instance, the stack may have 8 electrically conductive levels, 16 electrically conductive levels, 32 electrically conductive gate levels, 64 of electrically conductive levels, etc.
The stack is over an etchstop material 14, which is supported by a base 12. A break is provided between the etchstop material 14 and the base 12 to indicate that there may be additional materials and/or integrated circuit structures between the base and the etchstop material. The etchstop material may comprise, for example, aluminum oxide.
The base 12 may comprise semiconductor material; and may, for example, comprise, consist essentially of, or consist of monocrystalline silicon. The base 12 may be referred to as a semiconductor substrate. The term “semiconductor substrate” means any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductor substrates described above. In some applications, the base 12 may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit fabrication. Such materials may include, for example, one or more of refractory metal materials, barrier materials, diffusion materials, insulator materials, etc.
A hardmask material 22 is over stack 16, and a carbon-containing material 24 is over the hardmask material. Hardmask material 22 may comprise, for example, silicon nitride. The carbon-containing material 24 may comprise, for example, amorphous carbon.
FIG. 2 shows a patterned mask 26 provided over material 24. The mask defines an opening 28 which is patterned into materials 22 and 24; and such opening is then extended through stack 16 with an etch. The mask 26 may comprise a lithographic mask (e.g., photolithographically-patterned photoresist), or a mask formed with sub-lithographic processing (e.g., pitch multiplication methodologies).
Numerous problems are encountered in extending opening 28 into the stack 16. For instance, divots (or notches) 30 form where over-etching of dielectric material of levels 18 has occurred; bowing 32 (or other anomalies in the overall shape of the opening) occur, and excessive narrowing 34 occurs at the base of the opening. Such problems become increasing severe with increasing aspect ratios associated with higher levels of integration. It would be desired to develop methods which alleviate or prevent some or all of the problems described with reference to FIG. 2.